> For the complete documentation index, see [llms.txt](https://zeju.gitbook.io/lcm-team/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://zeju.gitbook.io/lcm-team/forgeeda/dataset.md).

# Dataset

### Overview

ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post- mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development.

<figure><img src="/files/VKlUKPBp9lmSkWeUHdea" alt=""><figcaption></figcaption></figure>

### RTL Code Repository

We use the RTL code repositories in DeepCircuitX.&#x20;

[Other modality information](/lcm-team/deepcircuitx/other-modality-information.md#rtl-code)

```
`timescale 1ns / 1ps

module alu(
    input [31:0] Operand1,
    input [31:0] Operand2,
    input [3:0] OPCODE,
    output reg [31:0] result
    );

	always@(*) begin

    case(OPCODE)
    4'b0000:
	result = Operand1 + Operand2;//ALU_Addition
    4'b0001:
	result = Operand1 - Operand2;//ALU_Substraction
    4'b0010:
	result = Operand1 * Operand2;//ALU_Multiplication
    4'b0011:
	result = Operand1 & Operand2;//ALU_AND
    4'b0100:
	result = Operand1 | Operand2;//ALU_OR
    4'b0110:
	result = Operand1 ^ Operand2;//ALU_XOR
    4'b0111:
	result = !Operand1;//ALU_NOT
    4'b1000:
	result = Operand1 << 1;//ALU_Left_Shift
	4'b1001:
	result = Operand1 >> 1;//ALU_right_Shift
	default:
	result = 32'b0;
    endcase
    end



endmodule
```

### Post-Mapping Netlist

We employ Synopsys Design Compiler ® and 12nm Process Design Kit (PDK) to synthesize RTL code repositories into post-mapped (PM) netlists, along with detailed synthesis reports.

[Other modality information](/lcm-team/deepcircuitx/other-modality-information.md#post-mapping-netlist)

````
```verilog
module alu ();
input OPCODE[0], OPCODE[1], OPCODE[2], OPCODE[3], Operand1[0], Operand1[10], Operand1[11], Operand1[12], Operand1[13], Operand1[14], Operand1[15], Operand1[16], Operand1[17], Operand1[18], Operand1[19], Operand1[1], Operand1[20], Operand1[21], Operand1[22], Operand1[23], Operand1[24], Operand1[25], Operand1[26], Operand1[27], Operand1[28], Operand1[29], Operand1[2], Operand1[30], Operand1[31], Operand1[3], Operand1[4], Operand1[5], Operand1[6], Operand1[7], Operand1[8], Operand1[9], Operand2[0], Operand2[10], Operand2[11], Operand2[12], Operand2[13], Operand2[14], Operand2[15], Operand2[16], Operand2[17], Operand2[18], Operand2[19], Operand2[1], Operand2[20], Operand2[21], Operand2[22], Operand2[23], Operand2[24], Operand2[25], Operand2[26], Operand2[27], Operand2[28], Operand2[29], Operand2[2], Operand2[30], Operand2[31], Operand2[3], Operand2[4], Operand2[5], Operand2[6], Operand2[7], Operand2[8], Operand2[9], ;
output U4474, U4486, U4498, U4510, U4522, U4534, U4546, U4558, U4851, U5091, U5108, U5326, U5531, U5736, U5928, U6118, U6295, U6470, U6630, U6798, U6945, U6958, U7109, U7245, U7408, U7547, U7681, U7800, U7917, U8019, U8121, U8531, ;
sky130_fd_sc_hd__nor2_2 U4472_Cell ( .A(U8535), .B(U4473), .Y(U4472) );
sky130_fd_sc_hd__nor2_4 U4473_Cell ( .A(U8535), .B(U8584), .Y(U4473) );
...
sky130_fd_sc_hd__clkinv_1 U8585_Cell ( .A(U8586), .Y(U8585) );
sky130_fd_sc_hd__nand3_1 U8586_Cell ( .A(OPCODE[0]), .B(U8587), .C(OPCODE[1]), .Y(U8586) );
sky130_fd_sc_hd__nor2_1 U8587_Cell ( .A(OPCODE[3]), .B(OPCODE[2]), .Y(U8587) );
endmodule

```
````

### Placed Netlist

We utilize Cadence Innovus ® to carry out the floorplanning and placement steps in the ASIC physical design flow.&#x20;

The placed netlists will be released soon.&#x20;

### And-Inverter Graph (AIG)

We begin by converting PM netlists, based on the standard cell library in the PDK, into And-Inverter Graphs (AIGs) using the ABC tool.&#x20;

{% file src="/files/hpdJHTtau0vkqqonCVmg" %}

### Sub-AIG

We also provide the sub-AIGs for model training, which are randomly extracted sub-circuits with 500- 5,000 nodes.&#x20;

{% file src="/files/5lMVTxerVNj9NGhvo0lG" %}