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  • DeepCircuitX
    • Introduction
    • Source RTL code
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    • RTL-Language Data for LLM Finetune
    • Data for PPA prediction
    • Tasks, experiments and results
      • LLM Finetune Results
      • PPA Prediction Results
  • ForgeEDA
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PPA Prediction Results

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Last updated 2 months ago

We collect 146 RTL designs for training and 10 designs for testing, with these designs containing more than 10k cells after logic synthesis and closely resembling practical designs. To explore the data scalability of PPA prediction models, we sample the training dataset size to 10%, 50% and 100%.

We use three baselines for training our dataset:

[17] 1Sns’s not a synthesizer: a deep- learning-based synthesis predictor

[18] How good is your verilog rtl code? a quick answer from machine learning

[19] Masterrtl: A pre-synthesis ppa estimation framework for any rtl design

In comparison to the originally reported performance on simple benchmarks, these models exhibit diminished performance on designs more than 10k cells in our dataset. Therefore, how to accurately predict PPA of practical designs remains an opening question, necessitating further exploration in the EDA community.