LCM-Team
  • Datasets of Large Circuit Model
  • DeepCircuitX
    • Introduction
    • Source RTL code
    • RTL code annotations by GPT
    • Other modality information
    • RTL-Language Data for LLM Finetune
    • Data for PPA prediction
    • Tasks, experiments and results
      • LLM Finetune Results
      • PPA Prediction Results
  • ForgeEDA
    • Introduction
    • Data Preparation
    • Dataset
    • Practical Downstream Tasks
      • Practical EDA Applications
      • AI for EDA Applications
  • ForgeHLS
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  1. DeepCircuitX

Data for PPA prediction

PreviousRTL-Language Data for LLM FinetuneNextTasks, experiments and results

Last updated 3 months ago

We employ logic synthesis tools to transform the RTL code into netlist and record the reports about Power, Performance and Area (PPA). Our dataset could enable predicting PPA metrics based on RTL code.

Example for PPA prediction

Given a complete RTL repositories, train a model to predict the total dynamic power, number of cells and maximum path delay after logic synthesis using a specific standard library.

Ground Truth:

Metric
Feature
Number

Area

Number of cells

4,116

Power

Total dynamic power

23.8842 mW

Delay

Maximum path dalay

19.57 ns

789B
alu.v